How to use the CPLD board

The easiest way to create a complex digital circuit without having to learn a new language is to design it on a CAD. Xilinx provides a development environment that in addition to allowing the description of the device through the VHDL language (Very high speed .. Hardware Description Language) also allows to draw it through the composition of standard modules such as flip flops or logic gates. In order to program a CPLD you need a JTAG interface that must be connected between the USB of the PC and the CPLD card. The interface is called "XILINX Platform Cable USB", and can be easily purchased on ebay at reasonable prices. Instead, the program can be downloaded for free from the Xilinx website: www.xilinx.com You need to activate an account with your personal data before downloading. There are various versions compatible with the various operating systems, therefore it is necessary to first check which version is most suitable for your operating system. Here is a link that can help you in the choice:

https://www.xilinx.com/support/answers/54242.html

After the installation you have to make a project add the files you prefer to the project, there are two main alternatives; The schematic entry that is the one we will use for this first example or the VHDL. Do describe a device using VHDL you have to read at least one good book about the subject. As first book I can suggest you "Laboratory experiments using Xilinx XC95108 CPLD with Xilinx design and simulation software" from "James W.Stewart and Chao-Ying Wang" So for the schematic entry way you just have to start the program. Click on File then New project, give a name to the project and click the Next button. On the following page select the CPLD family XC9500XL and the specific device XC9572XL. Once the project is created select from main menu Project and then new source, in the opening page you have to select as input file Schematic and give it a name. An empty page will appear where you can draw your schematic adding the elements from the add button. You can find ground and Vcc connection under Add --> Symbol --> General Add the device, for example a shift register, add the wires is terminated you you have to decide what is an input and what is an output adding to all the used (external) pins a buffer need to link the io names to the actual CPLD's pins. Now you can connect the input buffer to the actual external ports of Murano. Port names are listed on the board as P1 to P44. As you can see from the picture the sequence to associate each buffer to each Murano's port pin is:

• Right click on the specific buffer.
• On the pop up window click new to add an attribute to that buffer.
• In the second pop up window associate to the attribute name LOC the attribute value,
  namely one of the pin available on Murano board (p1 to p44)
• Do the same thing with all the input or output buffer

You can also use the Constraint editor to achieve the same result but it's more complicated. The aim is anywhow to create a file named UCF (User Constraint File) that associate each buffer (input or output) to the actual port pin of your device. This is a feature that I personally find cool, since you can start welding the CPLD to the circuit with no worry about the port pins and decide later where to connect it to the internal circuit. So the port pin is not associated to the signal as could be natural to think but to it's signal buffer. In the picture you can see the serial input signal already associated to port pin P5 and the highlighted in red input buffer being associated to port pin p1.

So once you have associated each buffer to each CPLD pin you can save the schematic and implement to obtain the final .jed file that will be sent to Murano through the USB Xilinx interface. To do that and see the pocess running you have to select the design tab in the lower left column and hit the button process and then Implement Top Module. You will see some activity in the lower left column. Don't worry if you see some warning icons like in the image beside, what is important at the end that the process produce the .jed file indicated by the green check mark beside the Generate programming file phase. There should be also a report on the main screen that tells you if the "compilation" was succesfull and how many resources (ports and registers) used for this project.

Now we are ready to download the file to the board. Connect Murano to the usb power source, connect Platform Cable USB to Murano using the flat cable and the adapter to the Murano's JTAG port and connect the USB cable of the programmer to another USB port of the PC. The programmer's adapter LED should be green when Murano is powered. To send the file now select on the upper bar Tools and then Impact, namely the programmer application. Click on Boundary scan and then on Initialize chain At the end tou should see on the screen an Icon representing the CPLD in green, click yes to the pop up window and select the jed file. If you didn't change the name the file should have the same name of the project with the .jed. The CPLD icon should now turn green indicating that now the CPLD can be programmed with the associated .jed file. Right click on the green CPLD icon and select program. The downloading process takes a little while but then you are done. The CPLD became what you have just drawn on the computer screen.