Burano, the other Xilinx CPLD development board
Board description
Burano is a XC9536XL based development board. The CPLD of this board has less resources than the CPLD mounted on Murano, it has 36 macrocells and two function blocks. The board on the other hand, has some additional hardware. I followed the indications of some customers and I added two debounced switches, a reserved space for two optional decoded hexadecimal display digits (TIL311) and a jumper to select two different oscillatorīs frequency ranges by connecting two different capacitors to the RC oscillator. Ranges go roughly from 2 to 140 Hz with jumper in LO position, to 120Hz to 16KHz with jumper in HI position. 7 segment decoding and debouncing could also be implemented into the CPLD, but given the scarce resources I decided to save them for the hobbystīs purposes. The RC oscillator as well could seem an unusual choice, but again, the use of a crystal oscillator force the user, in many cases, to use some of the 36 D-FlipFlop just to reduce the oscillatorīs frequency. Anyway, there are still two other CLOCK inputs to which can connect your own possible oscillator. To the ones who asked me why I didnīt use the internal gates for the RC oscillators I say that there is no Schmidt-trigger gates in the CPLD , and Xilinx advise against the use of internal gates to build RC oscillators. The electrical characteristics are the same as the ones of Murano, itīs TTL compatible in input and in output even if the CPLD works at 3.3V. The card has also an LED that stays on when the card is not programmed or when the pin marked with the word "LED" is not used, otherwise it follows the logic state of that pin, or rather, it lights up when that pin is set to 1. The outputs of the two debounce buttons are not connected to any pin but can be connected to any pin via a cable with dupont connectors. To program the device you can follow the same procedure described in Muranoīs page.
The distance of the two pins array is a multiple of 2.54 mm. This allows the connection any standard 2.54 breadboard to the board as a kind of experimental "shield".
Manuals in english, german and italian available here: BURANO_EN BURANO_DE BURANO_IT
I encourage you all to send me some more suggestions and/or
comments to improve next board according to your
requirements.
Here is a table with all the experiments made so far with Burano CPLD board:
| Project name | VHDL file | Schematic | Description | Datasheet of peripherals | Photo and/or video |
|---|---|---|---|---|---|
| Seven segment decoder | DM9368.vhdl | Schematic (Eagle), Schematic (Xilinx), | This is not exactly an experiment with Burano but the circuit described here uses the same CPLD mounted on Burano. Itīs made up with a decoding VHDL file converted into a block, and then the block is used two times to decode the two nibbles of a whole byte into two seven segments decoding. See schematics. Of course the same can me done using Burano (and also with Murano) providing proper connections to two 7 segments display units. | XC9536XL | Video, Photo |
| Morse message trasmitter | Morse VHDL | UCF File | A VHDL File to let Burano generate Morse messages. This file cam be used with Murano as well, providing a pin change in the UCF File. Itīs not a flexible program and it might be improved to generate morse code from a text file. If you can do it, let me know and I will post the upgrade. | Same as above | Video, |
| HP HEDS-6300 encoder reader | VHDL | UCF | A VHDL File to let Burano read the position of an HP HEDS-6300 relative encoder. | Missing but coming soon | Photo |
